PP708B : Timing Controller for Analog TFT-LCD Module

General Description

This timing controller is a CMOS LSI controlling for various analog TFT-LCD panel (Stripe Type: 480x234, 400x234, 320x234, Delta Type: 160x234) at any company panel. It accepts video synchronization signal (composite sync) and provides all the necessary timing signals to control the LCD source and gate drivers. Built-in PLL sub-function with external VCO and low pass filter circuits produces system clock whick synchronizes input composite synchronization signal. Especially, the internal noise filter with more than 70taps is added to separate HSYNC(Horizontal Sync) and VSYNC(Vertical Sync) signal from CSYNC(Composite Sync) carried nose like TV signal.

It supported any company analog panel(including sharp panel) and small size delta type panel.

Resolution
Company
480x234
(Inch Model Name)
400x234
(Inch/Model Name)
320x234
(Inch/Model Name)
160x234
(Inch/Model Name)
Note
Samsung 7.0"/LTE700WQ   5.0"/LTS500Q1-CF3    
LG 7.0"/LB070W02 6.5"/LB065WQ2      
AU
(InnoLux)

7.0"/A070FW02
( 7.0"/AT070TN01 )

6.5¡±/A065GW01 5.6¡±/A056DN01 4.0¡±/A040CN01
3.5"/A035CN02
the same kinds
Thoshiba
(ProView)
7.0"/LTA070B410A
( 7.0"/PV07LCM-T )
      the same kinds
Sharp 8.0"/LQ080T5GG01S
7.0"/LQ070T3GG003

5.0"/LQ050T3GG01S
5.8"/LQ058T3GG01S
6.5¡±/LQ065T5GG22

     
PVI

8.0"/PW084XS2
7.0"/PW070XS1
7.0¡±¡±/PW070XU3

6.5"/PW065XS1

6.4"/PA060XS1
5.0"/PA050XS1

3.5"/PA035XS1
2.5"/PA025XS1

3.5", 2,5" is delta
type panel

Sanyo 8.0"/TM080WA
7.0"/TM070WA
       
Other

HanStar
7.0¡±/HSD070I651
Topsun
TS70WA0105

ADT
5.0¡±/ADT050-C30P
HanStar
HSD050I551
     

Freatures

(1) Master clock frequency

28.70 MHz 480x234x3 Pixels
23.97 MHz 400x234x3 Pixels
19.27 MHz 320x234x3 Pixels
19.27 MHz 160x234x3 Pixels

(2) Built-in Phase Comparator for PLL sub-function
- It creates the divide signal compared with CSYNC input.
- It need to use the external OP-Amp for LPF(Loop Filter) and VCO.
(Note) Refer to application circuit (Page 30).
(3) Built-in the Vertical Sync separator to get VSYNC from CSYNC input.
- It need not use the external circuit for Vertical Sync separation (slicer)
- Input is only CSYNC (Composite Sync Signal)
(4) Provides the control timing signal of LCD source and gate drivers.
All the necessary output signals to control the LCD source and gate driver is as follows:
- Source : HCLK1, HCLK2, HCLK3, STH1, STH2, OEH
- Gate : CPV, STV1, STV2, OEV1, OEV2, OEV3, MOD1, MOD2, FRP
(5) Provides the timing scan signals for Left / Right and Up / Down shift control.
(6) Provides Horizontal and vertical positions adjustment function.
- Horizontal: 1 sign bit and external RC delay
-> It is possible to control the start position on horizontal with detailed and largely
- Vertical : 3-bit (-4 ~ 3 lines: signed)
(7) Provides the several display mode ( Full, Normal, Zoom etc. ) .
- Full, Normal, Zoom1, Zoom2, Zoom3, Wide, Zoom Wide1, Zoom Wide2
(8) Provides Serial Communication
- CS, CLK, DATA
(9) NTSC/PAL system timing
- It has two types of method to select video (NTSC/PAL)
: Manual NTSC/PAL Selection or Auto NTSC/PAL Detection
- It outputs video detection signal whether video signal exits or not.
(10) It supports RGB pattern signal.
- It can use PLL clock or external clock (dot clock)
(11) Package: 48-TQFP
(12) Single power supply: 5.0Volts.
- Including Regulator (LDO: 5V to 3.3V)
- The output voltage of the signal related with panel will be 3.3V or 5.0V according to panel Logic voltage.

Applications

USB & PS2 Keyboard Encoder
General Purpose MCU

Block Diagram

Products/Packages

Park Number Package Type Data sheet
PP707B 48-TQFP  



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